An interpolator includes a category of circuits or systems that are typically used to adjust the phase of sampling clock signals in fine increments. An interpolator may be used in a receiver in a serial link, such as in a data recovery system, to adjust the phase of clock signals to enable alignment with data bit pulses included in an incoming asynchronous data stream. Another implementation may be for use in a microprocessor that receives input clock signals that have a frequency that differs from its core clock frequency. An interpolator in these implementations may be used to align the various clock signals to the core clock to provide for proper timing. An interpolator may be implemented according to several configurations, such as a current-controlled interpolator or voltage-controlled interpolator.
FIG. 1 is a schematic diagram of an example interpolator 100. The interpolator 100 includes a differential amplifier 102 that receives a first clock input signal, clk1 (and its inverse or complement signal, clk1n), and a differential amplifier 104 that receives a second clock input signal, clk2 (and its inverse or complement. signal, clk2n). The differential amplifiers 102 and 104 are coupled in a wired-OR configuration. The differential amplifier 102 includes transistors 106 and 108. Although shown using n-channel, metal-oxide semiconductor (NMOS) transistors, other transistor types and configurations may be used. Transistor 106 is coupled to a current source 122, the latter configured in one example as a diode-connected, p-channel, MOS (PMOS) transistor. The current source 122 is supplied by a voltage source, Vs. The drain terminal of transistor 106 is coupled to output terminal 109a, on which a complementary clock signal clkn is provided. The drain terminal of transistor 108 is coupled to output terminal 109b, on which a clock signal elk is provided. The differential amplifier 102 is also coupled to a current sink 114. The current sink 114 may be comprised of a plurality of parallel-configured transistors (e.g., NMOS) 116. At any given time the total number of transistors 116 that are activated may vary from zero to a total of N transistors 116.
The differential amplifier 104 is configured similarly to the differential amplifier 102, and includes transistors 110 and 112. The transistor 112 is coupled to a current source 124, which is coupled to a voltage supply, Vs. The drain terminals of transistors 110 and 112 are coupled to output terminals 109a and 109b, respectively. The differential amplifier 104 is also coupled to current sink 118, which includes a plurality of parallel-configured transistors 120, similar to current sink 114.
In operation, the interpolator 100 receives clock signals from a clock source and shifts the clock signal phases in finite increments by adjusting the quantity of transistors 116 and 120 that are activated. For example, assuming input clock signals clk1 and clk2, clk2 being shifted 90-degrees in phase relative to clk1, the output clock signal clk on output terminal 109b would have a phase shift in the range of 0-90 degrees. The interpolator 100 accomplishes this function through the activation of a select quantity of transistors 116 and 120. For example, if all the transistors 116 of current sink 114 are activated (and transistors 120 are not activated), then the output clock signal elk on output terminal 109b will be equivalent in phase to clk1 (plus some fixed phase delay). If all the transistors 120 are activated (and no transistors 116 are activated), then the output clock signal clk on output terminal 109b will be equivalent in phase to clk2 (plus some fixed phase delay). Any other combination of activated transistors 116 and/or 120 results in an output clock signal clk that has a phase shifted somewhere between clk1 and clk2. Thus, the ability to shift the phase of the output clock signal clk to a phase ranging between that provided by clk1 and clk2 enables the output clock to be aligned with the incoming data.
One or more problems may arise with the interpolator architecture shown in FIG. 1. First, as the number of activated transistors 116 and/or 120 changes between current sinks 114 and 118, the gain of the differential amplifier transistor pairs changes, and hence the output swing varies. Additionally, as the number of activated current sink transistors 116 said/or 120 changes, the impedance to the rails varies. A variation in the impedance causes a shift in the output clock signal common mode. A common mode output refers to the average level round which the output swings. When the output swings, a stage that receives the output has some “trip-point.” The stage is then effected by this shift, which can cause an error in the interpolated result. Also, there is a power supply sensitivity corresponding to the operation of the interpolator circuit. In other words, as the power supply varies, so does the output level. Finally, as the number of current sink transistors changes, so does the slew rate and hence the fixed phase delay through the interpolator 100. These three problems, alone or in combination, may cause non-linear operation of the interpolator 100, hence reducing the ability to accurately align the delayed clock to the incoming data stream. For example, non-linearity of the interpolator 100 may lead to compression of the interpolator range and introduce jitter.
Additional problems of conventional interpolator architectures include the fact that such architectures often have a process dependence. That is, each chip that is manufactured possesses different characteristics that are often referred to as process variations. These variations can introduce errors in the interpolator. For example, as a result of some process variations, the transistors of 116 and 118 may not be identical. Thus, the desired weighting performance may not be realized between the two differential amplifiers 102 and 104.